Sequential equivalence checking based on structural similarities
نویسنده
چکیده
Checking the functional equivalence of sequential circuits is an important practical problem. Because general algorithms for solving this problem require a state-space traversal of the product machine, they are computationally expensive. In this paper, we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the statespace traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS’89 benchmarks.
منابع مشابه
Formal Equivalence Checking of Software Specifications
Ever-growing complexity is forcing logic design to move above the register transfer level (RTL). For example, functional specifications are being written in software. These specifications are written for clarity, and are not optimized or intended for synthesis. Since the software is the target of functional validation, equivalence verification between the software specification and the RTL impl...
متن کاملEquivalence checking of combinational circuits using Boolean expression diagrams
The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression Dia...
متن کاملFormal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
A new approach to sequential verification of designs at different levels of abstraction by symbolic simulation is proposed. The automatic formal verification tool has been used for equivalence checking of structural descriptions at rt-level and their corresponding behavioral specifications. Gate-level results of a commercial synthesis tool have been compared to specifications at behavioral or s...
متن کاملAn ATPG-Based Framework for Verifying Sequential Equivalence
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. The BDDbased approaches for equivalence checking can easily run into memory explosion for such designs. With an attempt to hand...
متن کاملFormal sequential equivalence checking of digital systems by symbolic simulation
A new approach to sequential verification of designs at different levels of abstraction by symbolic simulation is proposed. The automatic formal verification tool has been used for equivalence checking of structural descriptions at rt-level and their corresponding behavioral specifications. Gate-level results of a commercial synthesis tool have been compared to specifications at behavioral or s...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEEE Trans. on CAD of Integrated Circuits and Systems
دوره 19 شماره
صفحات -
تاریخ انتشار 2000